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june 2002 1 MICRF500 MICRF500 micrel MICRF500 uhf transceiver, 700mhz to 1000mhz final general description the MICRF500 is a single chip uhf transmitter and receiver intended for ism (industrial, scientific and medical) and srd (short range device) frequency bands from 808mhz to 915mhz with fsk data rates up to 128k baud. it can also be programmed for operation at other frequency bands in the 700mhz to 1000mhz range. the transmitter consists of a pll frequency synthesizer and a power amplifier. the frequency synthesizer consists of a voltage-controlled oscillator (vco), a crystal oscillator, dual- modulus prescaler, programmable frequency dividers and a phase-detector. the loop filter is external for flexibility and can be a simple passive circuit. the vco is a colpitts oscillator which requires an external resonator and varactor. fsk modulation can be applied externally to the vco. the synthesizer has two different n, m and a frequency dividers. fsk modulation can also be implemented by switching between these dividers (max. 2400bps). the lengths of the n and m and a registers are 12, 10 and 6 bits respectively. for all types of fsk modulation, data is entered at the dataixo pin (see application circuit). the output power of the power amplifier can be programmed to eight levels. a lock detect circuit detects when the pll is in lock. in receive mode the pll synthesizer generates the local oscillator (lo) signal. the n, m and a values that give the lo frequency are stored in the n0, m0 and a0 registers. the receiver is a zero intermediate frequency (if) type in order to make channel filtering possible with low-power integrated low-pass filters. the receiver consists of a low noise amplifier (lna) that drives a quadrature mixer pair. the mixer outputs feed two identical signal channels in phase quadrature. each channel includes a preamplifier, a third order sallen-key rc low pass filter that protects the following gyrator filter from strong adjacent channel signals and finally a limiter. the main channel filter is a gyrator capacitor implementation of a seven-pole elliptic low pass filter. the elliptic filter minimizes the total capacitance required for a given selectivity and dynamic range. the cut-off frequency of the sallen-key rc filter can be programmed to four different frequencies: 10khz, 30khz, 60khz and 200khz. an external resistor adjusts the cut-off frequency of the gyrator filter. the demodulator de- modulates the i and q channel outputs and produces a digital data output. it detects the relative phase of the i and the q channel signal. if the i channel signal lags the q channel, the fsk tone frequency lies above the lo frequency (data ??. if the i channel leads the q channel, the fsk tone lies below the lo frequency (data ??. the output of the receiver is available on the dataixo pin. a rssi (receive signal strength indicator) circuit indicates the received signal level. micrel, inc. ?1849 fortune drive ?san jose, ca 95131 ?usa ?tel + 1 (408) 944-0800 ?fax + 1 (408) 944-0970 ?http://www.mic rel.com a two pin serial interface is used to program the circuit. external components are necessary for rf input and output impedance matching and decoupling of power. other exter- nal components are the vco resonator circuit with varactor, crystal, feedback capacitors and components for fsk modu- lation with the vco, loop filter, bias resistors for the power amplifier and gyrator filters. a t/r switch can be implemented with 2-pin diodes. this gives maximum input sensitivity and transmit output power. features frequency range: 700mhz to 1000mhz modulation: fsk rf output power: 10dbm sensitivity (19.2k bauds, ber=10 -3 ): ?04dbm maximum data rate: 128k bauds applications telemetry remote metering wireless controller wireless data repeaters remote control systems wireless modem wireless security system ordering information part number junction temp. range package MICRF500blq ?0 c to +85 c 44-lead lqfp
MICRF500 micrel MICRF500 2 june 2002 pin description pin number pin name pin function 1 ifgnd if ground 2 ifvdd if power 3 ichout i-channel output 4 qchout q-channel output 5 oscvdd colpitts oscillator power 6 oscin colpitts oscillator input 7 oscgnd colpitts oscillator and substrate ground 8 gnd substrate ground 9 cmpout charge pump output 10 cmpr charge pump resistor input 11 mod output for vco modulation 12 xoscin crystal oscillator input 13 xoscout crystal oscillator output 14 ld_c external capacitor for lock detector 15 lockdet lock detector output 16 rssi received signal strength indicator output 17 pdext power down input (0=power down) 18 datac data filter capacitor 19 dataixo data input/output 20 clkin clock input for programming 21 regin data input for programming 22 digvdd digital circuitry power 23 diggnd digital circuitry ground pin configuration 12 rssi locdet ld_c xoscout xoscin pdext datac dataixo 13 14 15 16 17 18 19 1 2 3 4 5 6 7 8 9 10 11 ifgnd ifvdd ichout qchout oscvdd oscin oscgnd gnd cmpout cmpr mod digvdd regin clkin 20 21 22 33 32 31 30 29 28 27 26 25 24 23 mixervdd mixergnd lna_c rfgnd2 rfin rfvdd rfgnd rfout pabias pa_c diggnd 44 43 42 41 40 39 38 37 36 35 34 ifqinp ifqinn ichc qchc vb_ip mixqoutn mixqoutp ifiin mixioutp mixioutn ifiinp 44-pin lqfp (blq)
june 2002 3 MICRF500 MICRF500 micrel pin number pin name pin function 24 pa_c capacitor for slow ramp up/down of pa 25 pabias external bias resistor for power amplifier 26 rfout power amplifier output 27 rfgnd lna, pa and substrate ground 28 rfvdd lna and pa power 29 rfin low noise rf amplifier (lna) input 30 rfgnd2 lna first stage ground 31 lna_c external lna stabilizing capacitor 32 mixgnd mixer ground 33 mixvdd mixer power 34 mixioutp i-channel mixer positive output 35 mixioutn i-channel mixer negative output 36 ifiinp i-channel if amplifier positive input 37 ifiinn i-channel if amplifier negative input 38 mixqoutp q-channel mixer positive output 39 mixqoutn q-channel mixer negative output 40 ifqinp q-channel if amplifier positive input 41 ifqinn q-channel if amplifier negative input 42 ichc i-channel amplifier capacitor 43 qchc q-channel amplifier capacitor 44 vb_ip gyrator filter resistor pin description, cont?
MICRF500 micrel MICRF500 4 june 2002 electrical characteristics f ref = 850mhz, v dd = 2.5 to 3.4v, t = 25 c, unless otherwise specified . parameter condition min typ max units overall operating frequency 700 850 1000 mhz power down current < 1 2 a logic high input, v ih 70% v dd logic low input, v il 30% v dd dataixo, logic high output (v oh )i oh = ?00 a v dd -0.3 v dataixo, logic low output (v ol )i ol = 500 a 0.3 v lockdet, logic high output (v oh )i oh = ?00 a v dd -0.25 v lockdet, logic low output (v ol )i ol = 100 a 0.25 v clock/data frequency 10 mhz clock/data duty-cycle 25 75 % data setup to clock (rising edge) 25 ns vco and pll section prescaler divide ratio 64/65 reference frequency 40 mhz pll lock time (int. modulation) 4khz loop filter bandwidth 1 ms pll lock time (ext. modulation) 1khz loop filter bandwidth 4 ms rx ?(tx with pa on) switch time 1khz loop filter bandwidth 2.5 ms charge pump current 95/ 380 125/ 500 155/ 620 a transmit section f out = 850mhz output power r load = 100 ? , v dd = 3.0v 10 dbm transmit data rate (ext. modulation) note 4 19.2 128 kbauds transmit data rate (int. modulation) note 5 2.4 kbauds frequency deviation to modulation rate ratio unfiltered fsk 1.0 1.5 current consumption transmit mode 10 dbm, r load = 100 ? 50 ma absolute maximum ratings (note 1) maximum supply voltage (v dd ) ................................... +7v maximum npn reverse base-emitter voltage .......... +2.5v storage temperature range (t s ) ............ ?5 c to +150 c esd rating, note 3 operating ratings (note 2) supply voltage (v in ) ................................... +2.5v to +3.4v ambient temperature (t a ) ......................... ?0 c to +85 c package thermal resistance tqfp ( ja )-multilayer board ............................. 46.3 c/w
june 2002 5 MICRF500 MICRF500 micrel parameter condition min typ max units receive section f in = 850mhz receiver sensitivity (note 6) ber=10 -3 ?04 6 dbm input 1db compression level ?4 dbm input ip3 ?4 dbm input impedance 22.5-j28.5 ? rssi dynamic range 60 db rssi output voltage p in = ?00dbm 0.7 v p in = ?0dbm 2.1 v adjacent channel rejection: f c = 10khz 25khz channel spacing 26 db f c = 30khz 100khz channel spacing 37 db f c = 60khz 200khz channel spacing 45 db f c = 200khz 700khz channel spacing 48 db blocking immunity (1mhz) rc filter: f c = 10khz 66 db rc filter: f c = 30khz 61 rc filter: f c = 60khz 59 db rc filter: f c = 200khz 53 db maximum receiver bandwidth 175 khz receiver settling time 1ms current consumption gyrator filter f c = 60khz 12 ma receive mode current consumption xco 300 a note 1. exceeding the absolute maximum rating may damage the device. note 2. the device is not guaranteed to function outside its operating rating. note 3. devices are esd sensitive. handling precautions recommended. human body model, 1.5k in series with 100pf. note 4. modulation is applied to the vco and therefore the modulation cannot have any dc component. some kind of coding is needed to en sure that the modulation is dc free, e.g., manchester code or block code. with manchester code the bitrate is half the baudrate, but with 3b4b block code the bitrate is 3 / 4 of the baudrate. note 5: bitrate is the same as the baudrate. note 6: measured at 19.2k bauds and frequency deviation 25khz (external modulation), jitter of received data: < 45%.
MICRF500 micrel MICRF500 6 june 2002 functional diagram 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 logic 90 lna rc filters gyrator filters demod vco r s s i c o n t r o l i n t e r f a c e prescaler 64/65 control pa a1/a0 a-counter n-counter m-counter n1/n0 m1/m0 xco ld phase detector charge pump figure 1. transceiver internal blocks
june 2002 7 MICRF500 MICRF500 micrel typical application figure 2 shows an example of a transceiver with modulation applied to the vco. the vco and matching components are optimized for 869mhz. the inductors and trimming capaci- tors must have a good high frequency performance. the varactor ma4st-350-1141 is a single variable capaci- tance diode manufactured by macom. the pin diode bar63 is manufactured by siemens. l3 12n r15 1.5k ant-switch d3 bar63 d2 bar63 c12 1n ichout regin clkin dataix0 pdext rs si lock det qchout MICRF500 44-pin lqfp v dd vdd qchc 41 vb_ip 42 43 44 ichc ifqinn ifqinp mixqoutn mixqoutp ifiinn ifiinp mixioutn mixioutp ifgnd ifvdd ichout qchout oscvdd oscin oscgnd gnd cmpout cmpr mod c11 1n c10 1n c9 1n c8 4.7n c7 4.7n r6 8.2k mixer vdd mixer gnd lna_c rfgnd2 rfin rfvdd rfgnd rfout pabias pa_c diggnd xoscout xoscin ld_c lockdet rssi pdext datac dataix0 clkin regin digvdd 37 38 39 40 34 35 36 c26 10n 30 31 32 33 v dd v dd c5 47p c27 47p c25 470p c4 47p r14 1.5k c28 3.9p c29 47p l4 10n c32 5.6p c31 5.6p c6 47p l5 10n c30 47p r4 10 ? r5 10 ? l2 3.9n c33 47p vdd r3 10 ? c23 1n c24 1n c21 8.2p c22 22p 26 27 28 29 23 24 25 15 14 13 12 19 18 17 16 22 21 20 4 3 2 1 8 7 6 5 11 10 9 c16 100n r9 10k c15 4.7n c17 470p 10mhz c18 100n r12 1.5k r10 10k c19 470p r13 270k r11 150k c14 1.5-3p r8 39k d1 ma4st350 c13 5.6p r7 1.5k l1 12n r2 10 ? r1 10 ? vdd c2 47p c1 1n figure 2. application circuit
MICRF500 micrel MICRF500 8 june 2002 list of components component values component values component values r1 10 ? c6 47pf c25 470pf r2 10 ? c7 4.7nf c26 10nf r3 10 ? c8 4.7nf c27 47pf r4 10 ? c9 1nf c28 3.9pf r5 10 ? c10 1nf c29 47pf r6 8.2k ? c11 1nf c30 47pf r7 1.5k ? c12 1nf c31 5.6pf r8 39k ? c13 5.6pf c32 5.6pf r9 10k ? c14 1.5pf-3pf c33 47pf r10 10k ? c15 4.7nf l1 12nh r11 150k ? c16 68nf l2 3.9nh r12 1.5k ? c17 470pf l3 12nh r13 270k ? c18 100nf l4 10nh r14 1.5k ? c19 470pf l5 10nh r15 1.5k ? c20 3pf-10pf d1 ma4st-350-1141 c1 1nf c21 8.2pf d2 bar63 c2 47pf c22 22pf d3 bar63 c4 47pf c23 1nf crystal 10mhz c5 47pf c24 1nf
june 2002 9 MICRF500 MICRF500 micrel applications information vco and pll section the frequency synthesizer consists of a vco, crystal oscilla- tor, dual-modulus prescaler, programmable frequency divid- ers, phase-detector, charge pump, lock detector and an external loop filter. the dual-modulus prescaler divides the vco-frequency by 64/65. this mode is controlled by the a- divider. there are two sets of m, n and a-frequency dividers. using both sets in transmit mode, fsk can be implemented by switching between those two sets. the phase-detector is a frequency/phase detector with back slash pulses to mini- mize phase noise. the vco, crystal oscillator, charge pump, lock detector and the loop filter will be described in detail below. voltage controlled oscillator (vco) vdd pin 5 pin 6 c13 c14 1.5-3p d1 ma4st350 r7 1.5k 5.6p l1 12nh r8 39k loopfilter_output pin 7 oscout figure 3. vco the circuit schematic of the vco with external components is shown in figure 3. the vco is basically a colpitts oscilla- tor. the oscillator has an external resonator and varactor. the resonator consists of inductor l1 and the series connec- tion of capacitor c13, the internal capacitance and the capacitance of the varactor. the capacitance of the varactor (d1) decreases as the input voltage increases. the vco frequency will therefore increase as the input voltage in- creases. the vco has a positive gain (mhz/volt). the vco frequency is tuned by varying the trimming capacitor c13. if the value of capacitor c13 becomes too small the amplitude of the vco signal decreases, which leads to lower output power. the layout of the vco is very critical. the external compo- nents should be placed as close to the input pin (pin 6) as possible. ground vias should be next to component pads. crystal oscillator the crystal oscillator is the reference for the rf output frequency as well as for the lo frequency in the receiver. the crystal oscillator is a very critical block since very good phase and frequency stability is required. the schematic of the crystal oscillator with external components for 10mhz is shown in figure 4. these components are optimized for a crystal with 15pf load capacitance. digv dd c21 8p2 c20 3-10p 10mhz c22 22p pin 12 pin 13 xoscout diggnd figure 4. crystal oscillator the crystal oscillator is tuned by varying the trimming capaci- tor c20. the drift of the rf frequency is the same as the drift of crystal frequency when measured in ppm. the total differ- ence in ppm, ? f(ppm), between the tuned rf frequency and the drifted frequency is given by: ? f(ppm) = s t x ? t + n x ? t where: s t is the total temperature coefficient of the oscillator frequency (due to crystal and components) in ppm c. ? t is the change in temperature from room temperature, at which the crystal was tuned. n is the ageing in ppm/year. ? t is the time (in years) elapsed since the transceiver was last tuned. the demodulator will not be able to decode data when ? f(hz) = ? f(ppm) x f rf is larger than the fsk frequency deviation. for small frequency deviations, the crystal should be pre-aged, and should have a small temperature coeffi- cient. the circuit has been tested with a 10mhz crystal, but other crystal frequencies can be used as well. prestart of xco the start-up time of a crystal oscillator is typically some milliseconds. therefore, to save current consumption, the MICRF500 circuit has been designed so that the xco is turned on before any other circuit block. during start-up the xco amplitude will eventually reach a sufficient level to trigger the m-counter. after counting two m-counter output pulses the rest of the circuit will be turned on. the current consumption during the prestart period is approximately 300 a. lock detector the MICRF500 circuit has a lock detector feature that indi- cates whether the pll is in lock or not. a logic high on pin 15 (lockdet) means that the pll is in lock. the phase detector output is converted into a voltage that is filtered by the external capacitor c23, connected to pin 14, ldc. the resulting dc voltage is compared to a reference window set by bits ref0 ref5. the reference window can be stepped up/down linearly between 0v, ref0 ref5 =1, and ref0 ref5=0, which gives the highest value (dc voltage) of the reference window. the size of the window can either be equal to two (ref6 = 1) reference steps or four reference steps (ref6 = 0).
MICRF500 micrel MICRF500 10 june 2002 the bit setting that corresponds to lock can vary, depending on temperature, loop filter and type of varactor. therefore, the lock detect circuit needs to be calibrated regularly by a software routine that finds the correct bit setting, by running through all combinations of bits ref0 ref5. depending on the size of the reference window, there will be several bit combinations that show lock. for instance, with a large reference window, as much as five bit combinations can make the lock detector show lock. to have the maximum robustness to noise, the third of the bit settings should be chosen. charge pump the charge pump can be programmed to four different modes with two currents, 125 a and 500 a. bit 70 and 71 in the control word (cpmp1 and cpmp0) controls the operation. the four modes are: 1. cpmp1 = 0 current is constant 125 a. used in cpmp0 = 0 applications where short pll lock time is of no big importance. 2. cpmp1 = 0 current is constant 500 a. used in cpmp0 = 1 applications where a short pll lock time is important, e.g., internal modula- tion. see modulation inside pll section. 3. cpmp1 = 1 current is 500 a when pll is out of cpmp0 = 0 lock and 125 a when it is in lock. controlled by lockdet (pin 15). lock time is halved. see modulation outside pll section. 4. cpmp1 = 1 same as above in tx. in rx the current cpmp0 = 1 is 500 a. used when using dual-loop filters. see modulation outside pll dual-loop filters section. tuning of vco and xco there are two circuit blocks that may need tuning, the vco and the crystal oscillator. vco tuning tune the trimming capacitor in vco resonator until the pll is in lock and the charge pump output voltage (loop filter voltage) is around the mid-point of the supply rails. this is particularly important when using vco modulation. the gain curve of the vco (mhz/volt) is not linear and the gain will therefore vary with loop voltage. this means that the fsk frequency deviation also varies with loop voltage. it is therefore important to trim the loop voltage to the same value from circuit to circuit. when using internal modulation, tuning the vco can be omitted as long as the vco gain is large enough to allow the pll to handle variations in process parameters and tempera- ture without going out of lock. xco tuning tune the trimming capacitor in the crystal oscillator to the precise desired receive frequency. it is not possible to tune the crystal oscillator over a large frequency range. n, m and a values must therefore be chosen to give a rf frequency very close to the desired frequency. because of the small tuning range the vco will not go out of lock when tuning the crystal oscillator. fsk modulation the circuit has two sets of frequency dividers a0, n0, m0 and a1, n1, m1. the frequency dividers are programmed via the control word. a0, n0, m0 are to be programmed with the receive frequency and are used in receive mode. there are three ways of implementing fsk: fsk modulation can be applied to the vco. this way of implementing fsk modulation is ex- plained more in detail in the next section. the values corresponding to the transmit frequency should be programmed in dividers a1, n1 and m1. pin dataixo must be kept in tri-state from the time tx-mode is entered until one starts sending data. fsk modulation by switching between the two sets of a, n and m dividers. a, n and m values corresponding to the receive frequency and both transmit frequencies have to be found. in transmit the values corresponding to data 0 should be programmed in dividers a0, n0 and m0, and the values corresponding to data 1 should be programmed in dividers a1, n1 and m1. fsk modulation by adding/subtracting 1 to divider a1. the frequency deviation will be equal to the comparison frequency. the values corresponding to the transmit frequency should be programmed in dividers a1, n1 and m1. for all types of fsk modulation, data is entered at the dataixo pin. loop filter the design of the loop filter is of great importance for optimizing parameters like modulation rate, pll lock time, bandwidth and phase noise. low bitrates will allow modula- tion inside the pll, which means the loop will lock on different frequency for 1s and 0s. this can be implemented by switch- ing the internal dividers (m, n and a). higher modulation rates (above 2400bps) imply implementa- tion of modulation outside the pll. this can be implemented by applying the modulation directly to the vco. loop filter values can be found using an appropriate software program. modulation inside pll a fast pll requires a loop filter with relatively high bandwidth. if a second order loop filter is chosen, it may not give adequate attenuation of the comparison frequency. there- fore in the following example a third order loop filter is chosen.
june 2002 11 MICRF500 MICRF500 micrel example 1: radio frequency f rf 868mhz comparison frequency f c 100khz loop bandwidth bw 3.8khz vco gain k o 30mhz/v phase comparator gain k d 500 a/rad phase margin j 62 breakthrough suppression a 20db the component values will be: c116 22n r109 10k c101 100p out r101 33k in c115 1n figure 5. third order loop filter with this loop filter, internal modulation up to 2400bps is possible. the pll lock time from power-down to rx will be approximately 1ms. modulation outside pll (closed loop) when modulation is applied outside the pll, it means that the pll should not track the changes in the loop due to the modulation signal. a loop filter with relatively low bandwidth is therefore necessary. the exact bandwidth will depend on the actual modulation rate. because the loop bandwidth will be significantly lower than the comparison frequency, a second order loop filter will normally give adequate attenua- tion of the comparison frequency. if not, a third order loop filter may give the extra attenuation needed. example 2: radio frequency f rf 868mhz comparison frequency f c 140khz loop bandwidth bw 900hz vco gain k o 30mhz/v phase comparator gain k d 125 a/rad phase margin j 61 the component values will be: c16 68n r9 10k r10 10k out in c15 4.7n cmpr figure 6. second order loop filter data rates above approximately 19200baud (including manchester coding) can be used with this loop filter without significant tracking of the modulating signal. pll lock time will be approximately 4ms. if a faster pll lock time is wanted, the charge pump can be made to deliver a current of 500 a per unit phase error, while an open drain nmos on chip (pin 10, cmpr) switches in a second damping resistor (r10) to ground as shown in figure 6. once locked on the correct frequency, the pll automati- cally returns to standard low noise operation (charge pump current: 125 a/rad). if correct settings have been made in the control word (cpmp1 = 1, cpmp0 = 0), the fast locking feature is activated and will reduce pll lock time by a factor of two without affecting the phase margin in the loop. components c17, c18 c19, r11, r12 and r13 (see applica- tion circuit) are necessary if fsk modulation is applied to the vco. data entered at the dataixo pin will then be fed through the mod pin (pin 11) which is a current output. the pin sources a current of 50 a when logic 1 is entered at the dataixo and drains the current for logic 0. the capacitance of c17 will set the order of filtering of the baseband signal. a large capacitance will give a slow ramp-up and therefore a high order of filtering of the baseband signal, while a small capacitance gives a fast ramp-up, which in turn also gives a broader frequency spectrum. resistors r11 and r12 set the frequency deviation. if c18 is large compared to c17, the frequency deviation will be large. r13 should be large to avoid influencing the loop filter. pin dataixo must be kept in tri-state from the time tx-mode is entered until one starts sending data. modulation outside pll, dual-loop filters modulation outside the pll requires a loop filter with a relatively low bandwidth compared to the modulation rate. this results in a relatively long loop lock time. in applications where modulation is applied to the vco, but at the same time a short start-up time from power down to receive mode is needed, dual-loop filters can be implemented. figure 7 shows how to implement dual-loop filters. r109 10k r102 33k r8 89k r9 10k r10 10k pin4 pin10 pin9 towards_vco cmpout dfc c16 68n c15 4.7n c116 1n c115 22n c103 100p flc figure 7. dual-loop filters the loop filter used in transmit mode is made up of c15, c16, r9 and r10. the fast lock feature is also included (internal nmos controlled by flc, fast lock control). this filter is automatically switched in/out by an internal nmos at pin 4, qchout, which is controlled by dfc (dual filter control). bits outs2, outs1, outs0 must be set to 110. when qchout is used to switch the tx loop filter to ground, neither qchout nor ichout can be used as test pins to look at the different receiver signals. the receive mode loop filter comprises c115, c116, r109, r101 and c101. modulation outside pll (open loop) in this mode the charge pump output is tri-stated. the loop is open and will therefore not track the modulation. this means that the loop filter can have a relatively high bandwidth, which give short switching times. however, the loop voltage will decrease with time due to current leakage. the transmit time
MICRF500 micrel MICRF500 12 june 2002 will therefore be limited and is dependent on the bandwidth of the loop filter. high bandwidth gives low capacitor values and the loop voltage will decrease faster, which gives a shorter transmit time. the loop is closed until the pll is locked on the desired frequency and the power amplifier is turned on. the loop immediately opens when the modulation starts. the loop will not track the modulation, but the modulation still needs to be dc free due to the ac coupling in the modulation network. transmit power amplifier (pa) the power amplifier is biased in class ab. the last stage has an open collector, and an external load inductor (l2) is therefore necessary. the dc current in the amplifier is adjusted with an external bias resistor (r14). a good starting point when designing the pa is a 1.5k ? bias resistor which gives a bias current of approximately 50 a. this will give a bias current in the last stage of about 15ma. the impedance matching circuit will depend on the type of antenna used, but should be designed for maximum output power. for maximum output power the load seen by the pa must be resistive and should be about 100 ? . the output power is programmable in eight steps, with approximately 3db between each step. this is controlled by bits pa2 - pa0. to prevent spurious components from being transmitted the pa should be switched on/off slowly, by allowing the bias current to ramp up/down at a rate determined by the external capacitor c25 connected to pin 24. the ramp up/down current is typically 1.1 a, which makes the on/off rate for a 3.0v power supply 2.6 s/pf. turning the pa on/off affects the pll. therefore the on/off rate must be adjusted to the pll bandwidth. pa buffer a buffer amplifier is connected between the vco and the pa to ensure that the input signal of the pa has sufficient amplitude to achieve the desired output power. this buffer can be bypassed by setting the bit gc to 0. receive front end (lna and mixers) a low noise amplifier in rf receivers is used to boost the incoming signal prior to the frequency conversion process. this is important in order to prevent mixer noise from domi- nating the overall front end noise performance. the lna is a two-stage amplifier and has a nominal gain of 23db at 900mhz. the lna has a dc feedback loop, which provides bias for the lna. the external capacitor c26 decouples and stabilizes the overall dc feedback loop, which has a large low frequency loop gain. figure 8 shows the input impedance of the lna. input matching is very important to get high receive sensitivity. the lna can be bypassed by setting bit bylna to 1 . this is useful for very strong signal levels. the mixers have a gain of about 12db at 900mhz. the differential outputs of the mixers are available at pins 34, 35 and at pins 38, 39. the output impedance of each mixer is about 15k ? . figure 8. input impedance sallen-key filter and preamplifier each channel includes a preamplifier and a prefilter, which is a three-pole elliptic sallen-key low pass filter with 20db stopband attenuation. it protects the following gyrator filter from strong adjacent channel signals. the preamplifier has a gain of 20db when bit gc = 0 and 30db when bit gc = 1. the output voltage swing is about 200mv pp for the 30db gain setting and 1v pp for the 20db gain setting. the third order sallen-key low pass filter is programmable to four different cut-off frequencies according to the table below: fc1 fc0 cut-off frequency recommended (khz) channel spacing 0 0 10 2.5 25 0 1 30 7.5 100 1 0 60 15 200 1 1 200 50 700 for the 10khz cut-off frequency the first pole must be gener- ated externally by connecting a 820pf capacitor between the outputs of each mixer. for the 30khz cut-off frequency a 68pf capacitor is needed between the outputs. as the cut-off frequency of the gyrator filter can be set by varying an external resistor, the optimum channel spacing will depend on the cut-off frequencies of the sallen-key filter. the table above shows the recommended channel spacing depending on the different bit settings. gyrator filter the main channel filter is a gyrator capacitor implementation of a seven-pole elliptic low pass filter. the elliptic filter minimizes the total capacitance required for a given selectiv- ity and dynamic range. an external resistor can adjust the cut- off frequency of the gyrator filter. the table below show how the cut-off frequency varies with bias resistor:
june 2002 13 MICRF500 MICRF500 micrel bias resistor (k ? ? ? ? ? ) cut-off frequency (khz) 2.2 175 6.8 70 8.2 55 15 30 30 14 47 8 the gyrator filter cut-off frequency should be chosen to be approximately the same as the cut-off frequency of the sallen-key filter. the maximum cut-off frequency of the gyrator filter is 175khz. cut-off frequency setting the cut-off frequency must be high enough to pass the received signal (frequency deviation + modulation). the minimum cut-off frequency is given by: f c(min) = f dev + baudrate/2 for a frequency deviation of f dev = 30khz and a baudrate of 20k baud, the minimum cut-off frequency is 40khz. bit setting fc1 = 1 and fc0 = 0, which gives a cut-off of (60 15) khz, would be the best choice. the gyrator filter bias resistor should therefore be 7.5k ? or 8.2 k ? , to set the gyrator filter cut-off frequency to approximately 60khz. the crystal tolerance must also be taken into account when selecting the receiver bandwidth. if the crystal has a tempera- ture tolerance of say 10ppm over the total temperature range, the incoming rf signal and the lo signal can theoreti- cally be 20ppm away from each other. the frequency deviation must always be larger than the maximum frequency drift for the demodulator to be able to demodulate the signal. the minimum frequency deviation (f devmin ) is equal to the baudrate, according to the specifica- tion on page 2. this means that the frequency deviation has to be at least equal to the baudrate plus the maximum frequency drift. the frequency deviation may therefore vary from the mini- mum frequency deviation to the minimum frequency devia- tion plus two times the maximum frequency drift. the mini- mum cut-off frequency when crystal tolerances are consid- ered is therefore given by: f cmin ' = ? f x 2 f devmin + baudrate/2 where ? f is the maximum frequency drift between the lo signal and the incoming rf signal due to crystal tolerances. a frequency drift of 20ppm is 8680hz at 434mhz. the frequency deviation must be higher than 28.68khz for a baudrate of 20k baud. the frequency deviation may then vary from 20khz, when the rf signal is 20ppm lower than the lo signal; to 37.36khz when the rf signal is 20ppm higher than the lo signal. the minimum cut-off frequency is therefore 47.36khz. limiter the limiter serves as a zero crossing detector, thus removing amplitude variations in the if signal, while retaining only the phase variations. the limiter outputs are ideally suited to measure the i-q phase difference, since its outputs are square waves with sharp edges. demodulator the demodulator demodulates the i and q channel outputs and produces a digital data output. it detects the relative phase difference between the i and the q channel signals. for every edge (positive and negative) of the i channel limiter output, the amplitude of the q channel limiter output is sampled, and vice versa. the output of the demodulator is available on the dataixo pin. the data output is therefore updated 4 times per cycle of the if signal. this also means that the maximum jitter of the data output is 1/(4* ? f) (valid only for zero frequency offsets). if the i channel signal lags the q channel, the fsk tone frequency lies above the lo frequency (data 1 ). if the i channel leads the q channel, the fsk tone lies below the lo frequency (data 0 ). the inputs and the output of the demodulator are filtered by first order rc low pass filters and then amplified by schmitt triggers to produce clean square waves. it is recommended for low bitrates (<10kbps) that an addi- tional capacitor is connected to pin 18 (datac) to decrease the bandwidth of the rx data signal filter. the bandwidth of the filter must be adjusted for the bitrate. this functionality is controlled by bit rxfilt. received signal strength indicator (rssi) the rssi provides a dc output voltage proportional to the strength of the rf input signal. a graph of a typical rssi response is shown in figure 9 (f dev = 30khz, gc=1). 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 vout (v) pin ( dbm ) figure 9. typical rssi characteristics this graph shows a range of 0.7v to 2.05v over a rf input range of 70db. the rssi can be used as a signal presence indicator. when a rf signal is received, the rssi output increases. this could be used to wake up circuitry that is normally in a sleep mode configuration to conserve battery life. another application for which the rssi could be used is to determine if transmit power can be reduced in a system. if the rssi detects a strong signal, it could tell the transmitter to reduce the transmit power to reduce current consumption.
MICRF500 micrel MICRF500 14 june 2002 programming a two-line bus is used to program the circuit; the two lines being clkin and regin. the 2-line serial bus interface allows control over the frequency dividers and the selective powering up of tx, rx and synthesizer circuit blocks. the interface consists of an 80-bit programming register. data is entered on the regin line with the most significant bit first. the first bit entered is called p1, the last one p80. the bits in the programming register are arranged as shown in table 1. p1 p6 p7 - p12 p13 p24 p25 p36 p37 p46 p47 p56 p57 p58 a1 a0 n1 n0 m1 m0 rxfilt pa2 p59 p60 p61 p62 p63 p64 p65 p66 pa1 pa0 gc bylna ref6 ref5 ref4 ref3 p67 p68 p69 p70 p71 p72 p73 p74 ref2 ref1 ref0 cpmp1 cpmp0 fc1 fc0 outs2 p75 p76 p77 p78 p79 p80 outs1 outs0 mod1 mod0 rt pu table 1. bit allocation
june 2002 15 MICRF500 MICRF500 micrel name description a1 frequency divider a1, 6 bits a0 frequency divider a0, 6 bits n1 frequency divider n1, 12 bits n0 frequency divider n0, 12 bits m1 frequency divider m1, 10 bits m0 frequency divider m0, 10 bits rxfilt 1=external capacitor for filtering of rx data signal pa2 gain setting in power amplifier pa1 pa2, pa1, pa0 = 0 : lowest output power pa0 pa2, pa1, pa0 = 1 : highest output power gc gain control in power amplifier buffer: 1=high gain gain control in preamplifier in receiver: 1=high gain bylna 1 = the lna is bypassed ref6 ref5 reference settings in lock detector ref4 ref3 all 0 s: highest reference ref2 all 1 s: lowest reference ref1 ref0 cpmp1 charge pump setting: cpmp1=0, cpmp0=0 : 125 a cpmp0 cpmp1=0, cpmp0=1 : 500 a cpmp1=1, cpmp0=0 : controlled by lockdet (ld) ld=0: 500 a, ld=1: 125 a cpmp1=1, cpmp0=1 : same as previous in tx. in rx the current is 500 a. fc1 active rc-filter settings fc1=0, fc0=0 : 10khz fc1=1, fc0=0 : 60khz fc0 fc1=0, fc0=1 : 30khz fc1=1, fc0=1 : 200khz outs2 i- and q-channel outs2 outs1 outs0 ichout qchout outs2 outs1 outs0 ichout qchout outs1 output select 0 0 0 high z high z 1 0 0 lim_qch gm_qch outs0 0 0 1 sk_ich sk_qch 1 0 1 gm_ich lim_ich 0 1 0 gm_ich gm_qch 1 1 0 high z dual lf 0 1 1 lim_ich lim_qch 111n _div m_div sk:_*:sallen-key filter output, gm_*:gyrator filter output, lim_*:limiter output, *_div:frequency divider output (for testing). 110 is for dual-loop filter applications, see modulation outside pll, dual-loop filters. mod1 mod1 = 0, mod0 = 0: fsk modulation can be applied to the vco mod0 mod1 = 0, mod0 = 1: fsk modulation can be applied to the vco: open loop modulation mod1 = 1, mod0 = 0: fsk modulation by switching between the two sets of dividers mod1 = 1, mod0 = 1: fsk modulation by adding/subtracting 1 to divider a1: f deviation = f comparison rt 0 = receive mode 1 = transmit mode pu 1 = power up, 0 = power down (when pu=1, power down is controlled by puext) table 2. bit description
MICRF500 micrel MICRF500 16 june 2002 6: a new control word is entered into the first register. a transition on the regin signal when clkin is high will now turn the power amplifier off. 7: when the power amplifier is turned off an internal load pulse is generated. the new control word is loaded into the parallel register and the circuit enters a new mode (in this case power down mode). clkin must go low after the internal load pulse is generated. as long as transitions on regin are avoided when clkin is high, a new control word can be clocked into the first register any time without affecting the operation of the transceiver. example 1. f rf = 869.0mhz, frequency deviation: 10khz, f xco = 10.00mhz. fsk modulation is implemented by switch- ing between dividers. a1 a0 n1 n0 m1 m0 tx 9 27 137 134 101 99 rx 50 50 135 135 100 100 rxfilt pa2 pa1 pa0 gc bylna tx011110 rx011110 ref6 ref5 ref4 ref3 ref2 ref1 tx000000 rx000000 ref0 cpmp1 cpmp0 fc1 fc0 outs2 tx010010 rx010010 outs1 outs0 mod1 mod0 rt pu tx001011 rx001001 binary form: (msb to the left): tx: 001001 011011 000010001001 000010000110 0001100101 0001100011 011110000000001010001011 rx: 110010 110010 000010000111 000010000111 0001100100 0001100100 01011110000000001010001001 when fsk modulation is implemented by switching between the different dividers a, n and m values corresponding to the receive frequency and both transmit frequencies have to be found. when fsk modulation is applied to the vco the pll is using the dividers a1, n1 and m1. when mod1 = 1 and mod0 = 0 it is possible to switch between the different dividers in the pll. dataixo controls the switching. when dataixo = 0 the pll uses dividers a0, n0 and m0. when dataixo = 1 the pll uses dividers a1, n1 and m1. switching between the different dividers can be used to implement fsk modulation. the n, m and a values can be calculated from the formula: f f m f 64 n a c xco rf == + where f c is the comparison frequency. the 80bit control word is first read into a shift-register, and is then loaded into a parallel register by a transition of the regin signal (positive or negative) when the clkin signal is high. the circuit then goes directly into the specified mode (receive, transmit, etc.). clkin 1234 5 6 7 regin load_int pa_c lockdet figure 10. timing of clkin, regin and the internal load_int and pa_c signals 1: the second last bit is clocked into the first shift register ( 1 ). 2: the last bit is clocked into the first shift register ( 1 ). 3: a transition on the regin signal generates an internal load pulse that loads the control word into the parallel register. the circuit enters the new mode (in this case tx-mode). the circuit stabilizes in the new mode. 4: when the clock signal goes low, the power amplifier (pa) is turned on slowly in order to minimize spurious components on the rf output signal. to be sure the pll is in lock before the pa is turned on, the pa should be turned on after lockdet has been set. the negative transition on the clock signal should come a minimum time of one period of the comparison frequency after the internal load pulse is generated. 5: the power amplifier is fully turned on.
june 2002 17 MICRF500 MICRF500 micrel example 2. f rf = 869.0mhz, f rf = 10.00mhz. fsk modula- tion is applied to the vco. a1 a0 n1 n0 m1 m0 tx 50 50 135 135 100 100 rx 50 50 135 135 100 100 rxfilt pa2 pa1 pa0 gc bylna tx011110 rx011110 ref6 ref5 ref4 ref3 ref2 ref1 tx000000 rx000000 ref0 cpmp1 cpmp0 fc1 fc0 outs2 tx001100 rx001100 outs1 outs0 mod1 mod0 rt pu tx000011 rx000001 binary form: (msb to the left): tx: 110010 110010 000010000111 000010000111 0001100100 0001100100 01011110000000010100000011 rx: 111011 111011 000010001110 000010001110 0001101010 0001101010 01011110000000010100000001 with modulation applied to the vco, a, n and m values corresponding to the receive frequency have to be found. the same set of a, n and m values are used in all modes.
MICRF500 micrel MICRF500 18 june 2002 package information 0.551 0.012 (14.0 0.3) 0.394 0.012 (10.0 0.3) 0.315 0.012 (8.0 0.3) 0.016 (0.4) 0.031 (0.8) 0.039 (1.0) 0.085 0.004 (2.15 0.1) 0.002 (0.05) 0.047 (1.2) 1 11 12 22 23 33 34 44 44-pin lqfp (blq) micrel, inc. 1849 fortune drive san jose, ca 95131 usa tel + 1 (408) 944-0800 fax + 1 (408) 944-0970 web http://www.micrel.com this information is believed to be accurate and reliable, however no responsibility is assumed by micrel for its use nor for an y infringement of patents or other rights of third parties resulting from its use. no license is granted by implication or otherwise under any patent or pat ent right of micrel, inc. ? 2002 micrel, incorporated

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